Scan latches themselves are well known. In particular, they are used for boundary scan testing which is a well established technique for checking the functionality of logic circuits and the interconnections of integrated circuits. A brief explanation of the technique follows by way of background to the invention.
FIG. 1 illustrates schematically an exemplary structure of an integrated circuit (IC) 2 including the basic elements required to perform boundary scan testing. The IC 2 contains functional logic circuitry 4, a plurality of boundary scan cells 6a,6b,6c,6d, and a test access port (TAP) controller 12. For normal functional operation of the IC 2 the functional logic circuitry 4 is linked to the boundary scan cells 6a to 6d via respective links 10a to 10d. The boundary scan cells 6a to 6d are also connected to respective external pin connections 8a,8b,8c,8d which allow the functional logic circuitry to be connected to other circuitry including other ICs. For the purpose of performing boundary scan testing the boundary scan cells 6a to 6d each additionally include a scan test circuit, the scan test circuits being connected in a chain via chain connections 14a,14b,14c,14d,14e, the chain beginning and ending at the TAP controller 12.
The boundary scan cells 6a to 6d are only provided for the purpose of performing boundary scan testing. In normal functional operation of the IC 2 the boundary scan cells 6a to 6d operate to provide a direct connection between the links 10a to 10d and the external pin connections 8a to 8d.
Therefore, as normal function mode is always entered upon reset of the TAP controller, the links 10a to 10d will always be connected directly to the external pin connections 8a to 8d upon reset.
A simple boundary scan test is intended to check integrity between each external pin connection 8a to 8d and a corresponding external pin connection on another IC. A simple implementation of a known boundary scan cell for use in a boundary scan test circuit capable of implementing this is illustrated in FIG. 2. Such a boundary scan cell is known from IEEE Standard 1149.1-1990. The boundary scan cells 6a to 6d can be constructed to operate such that signals can only be inputted to the functional logic circuitry 4, such that signals can only be outputted from the functional logic circuitry 4, or such that signals can be both inputted to and outputted from the functional logic circuitry 4. The following description considers the implementation where the boundary scan cells 6a to 6d can all only output signals from the functional logic circuitry 4.
The boundary scan cell of FIG. 2 comprises an input multiplexor 26a, an output multiplexor 18a and two latches 28a,40a. The input multiplexor 26a has as one of its inputs the signal DATAIN on line 10a and as its other input the signal SCANIN on line 14a. The input multiplexor is controlled by a signal TAPCONTROL1 on line 34. The output of the input multiplexor 26a on line 30a forms the input to the capture latch 28a, and the output of the latch 28a on line 16a forms the input to the update latch 40a on line 22a and the signal SCANOUT on line 14b. The latches 28a and 40a are respectively clocked by the signals TAPCLOCK1 and TAPCLOCK2 on lines 36 and 38 respectively. The output multiplexor 18a has as one of its inputs the signal DATAIN on line 10a and as its other input the output of the latch 40a on line 24a. The output multiplexor is controlled by a signal TAPCONTROL2 on line 22 and generates at its output the signal DATAOUT on line 8a. The signals TAPCONTROL1, TAPCONTROL2, TAPCLOCK1 and TAPCLOCK2 are all generated under the control of the TAP controller 12 and are all common to all the boundary scan cells 6a to 6d, although these signals and connections are not shown in FIG. 1 for reasons of clarity.
Two modes of operation of the IC 2 of FIG. 1 will now be described with reference to FIGS. 1 and 2. It will be appreciated that each of the boundary scan cells 6a to 6d contains a circuit similar to that shown in FIG. 2, with the various components and signal lines suffixed b,c,d appropriately.
In normal functional operation, the TAP controller 12 is inactive and the output multiplexor 18a will be controlled by the control signal TAPCONTROL2 on line 22 such that the signal DATAIN on line 10a is connected directly to the signal DATAOUT on line 8a. During such normal functional operation the control of the input multiplexor 26a is unimportant, and the clock signals TAPCLOCK1 and TAPCLOCK2 on lines 36 and 38 respectively will both preferably be inhibited.
When a boundary scan test is to be performed, the TAP controller 12 on IC2 controls the signal TAPCONTROL2 on line 22 such that the multiplexor 18a connects its input on line 24a from the output of the latch 40a to its output on line 8a. In order to carry out the boundary scan test it is necessary to place a known bit on each of the respective pin connections 8a to 8d. To achieve this the TAP controller controls the multiplexor 26a by means of the control signal TAPCONTROL1 on line 34 such that its output on line 30a is connected to its input on line 14a. The TAP controller 12 then serially outputs a sequence of test bits on line 14a under the control of the clock signal TAPCLOCK1 on line 36 such that the test bits are clocked through the latches 28a to 28d in sequence via the signal lines 14b to 14d. After a plurality of clock cycles (four in the example shown in FIG. 1 but normally a much larger number dependent on the number and type of pin connections 8a to 8d) of TAPCLOCK1 each of the nodes 31a to 31d will have a known test bit stored thereat by means of the respective latches 28a to 28d. The TAP controller then clocks the signal TAPCLOCK2 on line 38 such that the test bit on each node 31a to 31d appears on output lines 24a to 24d of latches 40a to 40d. Consequently the test bits appear on the respective external pin connections 8a to 8d. If the IC 2 is connected to similar boundary scan cells being configured to input signals to their respective IC and having a boundary scan test capability, then the TAP controllers controlling these input boundary scan cells can serially read their respective boundary scan cells so that a check can be carried out to ensure that the value written to a boundary scan cell by a particular TAP controller was successfully communicated to another boundary scan cell to which it is connected. In this manner the interconnections between various ICs can be tested.
It can be seen that the above technique allows the test to be carried out without the TAP controller 12 needing to account for the actual operation of the functional logic circuitry 4. The TAP controller only needs to know the number and type of boundary scan cells on the IC 2. The boundary scan testing technique is primarily intended for board testing.
FIG. 3 illustrates the state diagram of the TAP controller 12 of FIG. 1 as defined by IEEE Standard 1149.1-1990. The operation of the circuitry of FIG. 2 in performing a boundary scan test will now be described with the aid of the state diagram shown in FIG. 3.
During normal functional operation of the IC 2 the TAP controller 12 is in a test-logic-reset state S0. In this state the test logic is idle and the signal DATAIN on line 10a is connected directly to the signal DATAOUT on line 8a by means of the output multiplexor 18a under control of the signal TAPCONTROL2 on line 22. The TAP controller 12 is controlled by a master clock signal MCLOCK. The master clock MCLOCK is a buffered version of the clock TCK defined in IEEE Standard 1149.1-1990. Upon a test operation commencing, the TAP controller 12 will first move into a run-test/idle state S1.
If a boundary scan test is to be carried out the TAP controller 12 will, on the next cycle of MCLOCK, enter a select-scan state S2 and the control signal TAPCONTROL2 on line 22 will change state such that the output signal DATAOUT of the output multiplexor 18a on line 8a is connected directly to the signal on line 24a. On the next clock cycle of MCLOCK the TAP controller will enter a capture state S3. At this stage of the test the capture state is unimportant because no test data has yet been loaded into the scan test circuit.
On the next clock cycle of MCLOCK a shift state S4 is entered into. In this state the TAP controller produces a plurality of clock cycles constituting clock signal TAPCLOCK1 on line 36 whilst holding the signal TAPCONTROL1 on line 34 at a level such that the signal SCANIN on line 14a appears at the output 30a of the multiplexor 26a. In this way the test data is serially shifted into the test circuitry such that after a certain number n of clock cycles of TAPCLOCK1 (in this case four) the latches 28a,28b,28c,28d all have a known test bit on their respective outputs on nodes 31a to 31d. Hence for n cycles of the master clock MCLOCK the shift state S4 is retained. On the next cycle of the master clock an exit1 state S5 is entered. The state S5 is a temporary state and the TAP controller will normally move into an update state S8 on the next clock cycle of the master clock. The TAP controller could alternatively enter a pause state S6 followed by an exit2 state S7, but for reasons unconcerned with this invention and which are not explained herein.
Whilst in the update state S8 the TAP controller causes the output of the latch 40a to be updated by generating a clock cycle to constitute clocking the clock signal TAPCLOCK2 on line 38a once. The test data bit on the output node 31a of the latch 28a will therefore appear on the output of the latch 40a on the line 24a and consequently as the DATAOUT signal on line 8a. At this point of the test operation all the DATAOUT signals on lines 8a to 8d will have been updated. The pin connections 8a to 8d are, as mentioned previously, connected to respective pin connections on one or more other ICs. Therefore, after a short amount of time to allow for the propagation of the updated signal between the ICs (which may include propagation through buffering logic between the ICs), the updated signals on pin connections 8a to 8d will appear on the respective pin connections on one or more other ICs. The pin connections on the other ICs will be connected to boundary scan cells configured as input or input/output devices. It will be within the scope of a skilled person having reference to IEEE Standard 1149.1-1990 how such an input boundary scan cell will be implemented and such an input boundary scan cell will therefore not be described in detail herein. For the purposes of completing the description of a boundary scan test it will be assumed that the input boundary scan cell on the IC to which the IC 2 is connected is identical to the boundary scan cell of FIG. 2, with the difference that the pin connection of such other IC is connected as the DATAIN signal on line 10a. Therefore, for the purposes of the remainder of the description of the circuit of FIG. 2, it is assumed that the signal DATAIN on line 10a is a result to be checked. In other words, it will be assumed that after the previously described update operation is performed, a short time afterwards a result will be generated on line 10a.
On the next cycle of the master clock the TAP controller will once again enter the select scan state S2 and then on the next cycle will enter the capture state S3. In the capture state the latch 28a will be clocked once by the clock signal TAPCLOCK1 on line 36 whilst the multiplexor is controlled by the signal TAPCONTROL1 on line 34 such that the signal on line 10a appears on its output on line 30a. Thus the result generated in response to the update operation is captured on line 16a. The TAP controller then, on the next master clock cycle, enters the shift state S4 once more and the results captured on the outputs of the flip-flops 28a to 28d are serially clocked out to the TAP controller, under the control of clock signal TAPCLOCK1 on line 36. It can be appreciated that at the same time as the captured result is clocked out of the latches 28a to 28d a new set of test bits can be clocked into the latches 28a to 28d from the TAP controller. Consequently, the above described cycle of states from S2,S3,S4,S5,S8 and back to S2 can be repeated continuously.
Referring now to FIG. 4, an implementation of the latch 28a of FIG. 2 is shown. The latch 28a consists of two half-latches, or transparent latches, 44a and 46a. Each half-latch consists of a respective control node 48a,52a and a respective storage node 50a,54a. The clock signal TAPCLOCK1 on line 36 clocks the control node 52a of half-latch 46a whilst the inverse of the clock signal TAPCLOCK1, NOTTAPCLOCK1, clocks the control node 48a. It will be understood, as is well known in the art, that the clock signals TAPCLOCK1 and NOTTAPCLOCK1 could be non-overlapping clock signals, or alternatively circuitry in the control nodes 48a and 52a could take account of any possible overlap of the two clocks. The latch 40a of FIG. 2 similarly comprises two half-latches. It can therefore be seen that the circuit of FIG. 2 comprises four half-latches. To provide correct clock operation for both normal functional operation and for test purposes, the circuit of FIG. 2 requires a complex clocking scheme as will be understood from the description provided hereinabove with reference to FIGS. 2 and 3.
A scan latch which overcomes these problems is described in our copending application Ser. No. 08/519,051. That scan latch comprises a capture half latch having an input terminal connected to receive an input signal, a control terminal connected to receive a clock signal, and an intermediate output terminal; a release half latch having an input terminal connected to the intermediate output terminal of the capture half latch, a control terminal connected to receive a clock signal, and a scan output terminal; and an update half latch having an input terminal connected to the intermediate output terminal of the capture half latch, a control terminal connected to receive a clock signal, and a data output terminal.
A particularly advantageous implementation of the scan latch is where the clock signals provided to the capture half latch, release half latch and update half latch are derived from a common clock source, the release half latch and the update half latch receiving the inverse of the clock signal applied to the capture half latch.
The object of the present invention is to provide a half latch suitable for use in this type of scan latch.